A distributed border trap model based on tunneling between the semiconductor surface and trap states in the gate dielectric film is formulated to account for the observed frequency dispersion in the capacitance and conductance of Al 2 O 3 /InGaAs MOS devices biased in accumulation. The distributed circuit model is more physical and descriptive than previous lumped circuit border trap models in the literature. The distributed model correctly depicts the frequency dependence of both capacitance and conductance data in accumulation. A border trap volume density is extracted from the quantitative agreement with measured data.