The high electron mobility of compound semiconductor materials, arising from the combination of low effective mass and materials dependent intervalley scattering mechanisms, can result in high velocity and low backscatter electrons being injected at the source side of a III–V nMOSFET. In combination, these factors have the potential to meet the highly challenging performance metrics of the International Technology Roadmap for Semiconductors (ITRS) [1] beyond the 15 nm technology generation, in particular the need to reduce supply voltages towards 0.5 V. This paper highlights some challenges over and above those of developing a high quality dielectric/III–V semiconductor interface, specifically in the areas of scaled source/drain contact formation and channel materials and device architectures which have to be addressed if III–V MOSFETs are to be a credible solution to enable continued scaling of the ITRS beyond 2018.